Plasma display panel induction preventing system

ABSTRACT

A plasma display panel induction preventing system in which when a write or erasing pulse is impressed to a selected one of electrodes of a plasma display panel, those electrodes adjoining the selected electrode are clamped at a predetermined potential or an induced voltage canselling pulse opposite in polarity to the write or erasing pulse is impressed to the adjoining electrodes, thereby preventing undesired effects resulting from an induced voltage.

States Patent [191 Ilmea et al,

PLASMA DISPLAY PANEL INDUCTION PREVENTING SYSTEM Inventors: ShnzoIlmeda, Kakogawa; Hiroslhi lFuruta, Akashi; 'Ieruo Tuba, Akashi; HiroshiGoto, Akashi; IIiroyuki Ishizaki, Akashi, all of Japan Assignee: FujitsuLimited, Kawasaki, Japan Filed: June 28, 1973 Appl. No.: 374,622

Foreign Application Priority Data June 30, i972 Japan 47-65743 US. Cl.315/169 TV, 315/169 R Int. Cl. HOSb 37/00 Field of Search 315/169 TV,169 R References Cited UNITED STATES PATENTS ll/l965 Sack 315/169 TVNov. 26, 1974 3,573,542 4/l97l Mayer et al 315/169 R PrimaryExaminerHerman Karl Saalbach Assistant Examiner-Lawrence J. DahlAttorney, Agent, or Firm--Staas, Halsey & Gable [5 7] ABSTRACT A plasmadisplay panel induction preventing system in which when a write orerasing pulse is impressed to a selected one of electrodes of a plasmadisplay panel, those electrodes adjoining the selected electrode areclamped at a predetermined potential or an induced voltage cansellingpulse opposite in polarity t0 the write or erasing pulse is impressed tothe adjoining electrodes, thereby preventing undesired effects resultingfrom an induced voltage.

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PLAS l DISPLAY PANEL INDUCTION PREVENTING SYSTEM BACKGROUND OF THEINVENTION 1. Field of the Invention This invention relates to a systemfor preventing an induced voltage in a plasma display panel, and moreparticularly to a system for the prevention of undesired effectsresulting from a voltage which is induced in those electrodes adjacentto a selected electrode supplied with an address signal.

2. Description of the Prior Art In a plasma display panel, analternating sustain voltage is previously impressed to electrodes and anaddress voltage such as a write, erasing, read voltage or the like isimpressed to a selected one of the electrodes to produce or erase adischarge spot in a discharge cell at an intersecting point of theelectrodes. With the impression of such an address voltage, a voltage isinduced in electrodes adjacent to the selected electrode due to theinter-electrode capacity or the like. For example, in FIG. 1, byimpressing erasing pulses EX and EY shown in FIG. 2 to electrodes X3 andY3, a voltage identified by VA is impressed to a discharge cell A at theintersecting point of the electrodes X3 and Y3 and results in an erasingpulse EP which exceeds an erasing level EL, thereby to erase thedischarge spot at that intersecting point. In such a case, if theinter-electrode capacitance is taken as C1, if the earth capacity istaken as C2 and if the voltage impressed to the electrodes X3 and Y3 istaken as V], a voltage V2 given by the following equation is induced inelectrodes adjacent to the electrodes X3 and Y3:

V2 (Cl/Cl C2)VI The voltage V2 is usually about Vl/S to Vl/lO.Consequently, in some cases, a pulse EIX such as indicated by VXB inFIG. 2 which is induced by the erasing pulse EX is impressed to theelectrodes X2 and X4 adjacent to the electrode X3 and a voltageindicated by VB is applied to a half-selected cell B. Namely, a pulse EBabove the erasing level EL is impressed to the halfselected cell B dueto the induced pulse EIX and the erasing pulse EY applied to theelectrode Y3. Such a pulse EB exceeding the erasing level EL causes anerroneous erasure. This imposes a severe limitation on the range of theerasing pulses Ex and EY, and hence results in the reduction of theoperational margin. The same is true of other half-selected cells C, Dand E and the impression of the write, read or like pulse also presentsthe same problem as described above.

Further, such induction as mentioned above similarly occurs in electrodeterminal plates of the plasma display panel. This will hereinbelow bedescribed with reference to FIG. 3.

FIG. 3 shows associated structures of leads of X electrodes arranged ona plasma display panel 10. Reference numerals 11A and 11B designateterminal plates having a plurality of leads arranged on a flexible thinplate or the like, and reference characters X1, X2, X3, indicateelectrodes. Leads a1, a3, a5, of the terminal plate 11A are connected toodd-number electrodes X1, X3, X5, respectively and leads b2, b4, of theterminal plate 11B are connected to evennumber electrodes X2, X4,respectively. Where the electrodes are closely spaced apart fromadjacent ones, all the electrodes are connected to the leads of oneterminal plate. With such an arrangement, the impression of the addressvoltage such as a write, erasing, read or like voltage to a selected oneof the electrodes induces a voltage in each of the adjoining electrodesdue to the inter-electrode capacitance including the capacitance betweenadjacent leads.

FIG. 4 illustrates an equivalent circuit regarding the electrodes X1 toX4. Reference character C1 identifies the capacitance between adjacentones of the electrodes, C2 the earth capacitance and C0 the capacitancebetween adjacent ones of the oddor evennumber electrodes. For example,if a voltage V1 is impressed to the electrode X1, a voltage V2 expressedby the following equation is induced in the electrode X2 adjacent tothat X1:

and a voltage V3 given by the following equation is induced in theelectrode X3:

Since the ratioof C1 to C2 is usually about l:(3 to 10), the voltage V2is about 16 to 1/10]V1, and since C0 E 0.5C1, the voltage V3 is about[Vs to l/20]Vl. Accordingly, the discharge cells on the electrode X2,especially the discharge cell at the intersecting point of theelectrodes X2 and X3, that is, the so-called halfselected cell, islikely to perform an erroneous operation due to the induced voltage. [inthe electrode X3, the induced voltage is about one-half of that in theelectrode X2, and hence it does not present such a problem. Such aninduced voltage restricts the write, erasing, read and like operationswithin narrow limits to reduce the operational margin.

Incidently, an increase in the number of electrodes of the plasmadisplay panel causes an increase in the number of drivers included inperipheral circuits for driving, so that it is the practice in the artto build up a matrix circuit with drivers and mixers to thereby minimizethe increase in the number of the drivers with an increase in that ofthe electrodes. For driving the plasma display panel according to adiode-resistance matrix system, use is made of such a construction asdepicted in FIG. 5. Of electrodes 0, 1, 2, the electrode, for example,0, is selected by turning on a transistor Q11; off-transistors Q12 toQ18 and Q21; and on transistors Q22 to Q28. The electrodes 1 to 7, 9 to15, are clamped by the transistors 022 to Q28 at the ground potentialand the electrodes 8, l6, exhibit high impedance. The eletrodes 8, 16,which exhibit high impedance at this time, are arranged every eighthones of the electrodes, so that an induced voltage therein is very smalland negligible. A similar, modified circuit is in a form such as shownin FIG. 6. However, such a circuit necessitates the use of discreteparts as individual diodes. In order to employ a diode array ofintegrated construction for the diodes, it is necessary to arrange theelectrodes in the order of parenthesized numbers in FIG. 5 andinterconnect the diodes at one end. A modified form of the circuit inthis case is illustrated in FIG. 7. With this circuit construction,where the electrode 0 has been selected, the transistor Q21 is held inits off state and the adjoining electrodes 1, 2, 3, are not grounded andconsequently exhibit high impedance, presenting the problem of theinduced voltage.

A system of addressing with a matrix circuit employing charge storagediodes has an advantage in that power dissipation is small as comparedwith the aforesaid diode-resistor matrix system but a disadvantage inthat those electrodes adjacent to a selected one exhibit high impedanceat the time of the addressvoltage impression, whereby the problem of theinduced voltage is introduced.

SUMMARY OF THE INVENTION This invention is to provide a novel system forpreventing an induced voltage in a plasma display panel which is freefrom the aforesaid defects encountered in the prior art and which avoidstroubles resulting from a voltage induced in electrodes adjoining anelectrode impressed with an address signal voltage.

Briefly stated, this invention is featured in the following points:

I. When an address voltage is impressed to a selected one of theelectrodes of the plasma display panel, at least those electrodesadjacent to the selected one are clamped by a diode to a predeterminedpotential.

2. When an address voltage is impressed to a selected one of theelectrodes of the plasma display panel, a group of electrodes includingthe selected one is clamped by an impedance element at a predeterminedpotential.

3. Oddand even-number electrodes of the plasma display panel areconnected to leads of different terminal plates respectively. When anyof the oddor evennumber electrodes is selected, the evenor oddnumberelectrodes, respectively, are clamped at a predetermined potential.

4. Oddand even-number electrodes of the plasma display panel areconnected to leads of different terminal plates respectively. Conductorsconnected to the even-number electrodes are each arranged to extendbetween adjacent ones of the leads of the terminal plate for theodd-number electrodes and, in a similar manner, conductors connected tothe odd-number electrodes are each arranged to extend between adjacentones of the leads of the terminal plate for the evennumber electrodes.When any of the oddor evennumber electrodes has been selected, theevenor oddnumber electrodes, respectively, are clamped at apredetermined potential together with the conductors connected thereto.

5. A voltage opposite in polarity to an address voltage for theimpression to a selected one of the electrodes is impressed to thoseelectrodes adjacent the selected electrode simultaneously with theimpression of the former voltage.

The objects and advantages of this invention will become more apparentfrom the following description taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an electrode arrangementdiagram, for explaining a selected cell and half-selected cells;

FIG. 2 shows a series of waveforms, for explaining an erasing operationand an induced voltage trouble;

FIG. 3 is a diagram, for explaining the relation between electrodes andterminal plates of a plasma display panel;

FIG. 4 is an equivalent circuit diagram;

FIG. 5 is a circuit diagram illustrating the principal part of adiode-resistor matrix driving circuit of the prior art;

FIG. 6 is a circuit diagram of one part of the circuit diagram depictedin FIG. 5;

FIG. 7 is a circuit diagram of the principal part of a circuit in whichelectrodes in the circuit of FIG. 5 are connected in the order ofparenthesized numbers in FIG. 5;

FIGS. 8 and 9 are circuit diagrams of the principal parts of examples ofthis invention in which electrodes adjoining a selected one are clampedat a predetermined potential;

FIGS. 10 to 12 are diagrams illustrating other examples of thisinvention in which oddand even-number electrodes are clamped together;

FIG. 13 is a circuit diagram showing another example of this inventionin which electrodes are clamped by an impedance element at apredetermined potential at the time of addressing;

FIGS. 14 to 16 are circuit diagrams of the principal parts of otherexamples of this invention which prevents an induced voltage in a stateincluding tenninal plates;

FIGS. 17A and 17B are cross-sectional views taken on the line AA in FIG.16; and

FIG. 18 is a circuit diagram of the principal part of another example ofthis invention in which a voltage erasing an induced voltage isimpressed.

DESCRIPTION OF THE PREFERRED EMBODIMENTS In FIG. 8, there is depicted acircuit diagram of the principal part of one example of this invention,which is a drive circuit employing charge storage diodes CSD. A decoder20A is supplied with address signals 2", 2 and 2 and a decoder 20B issupplied with address signals 2 2 and 2 For example, an electrode 0 isselected by turning on a transistor Q11, off transistors O12, O13, andQ31 and on transistors O32, O33, Reference numerals 21A and 21Bdesignate inverters, and 22 indicates AND gates. The output 1 from theAND gates 22 turn on the transistors O21, O22, Accordingly, uponapplication of an inverted address signal 1 and a timing pulse T? to thetwo inputs of the AND gate 22, the transistor Q21 is turned on to permitflowing of a current in a circuit of the transistor Q11, a diode DP, acharge storage diode CSD and the transistor Q21 from a power source Va.At an instant when the timing pulse TP has become 0, a transistor O4 isturned on to flow a current for a backward recovery time of the diodeCSD, thereby impressing an address voltage such as a write, erasing,read or like voltage from power source V to the electrode 0. At thistime, since the transistors O32, O33, are in the on state due to thesignal 1 from the decoder 20A, electrodes 1 to 7, 9 to 15, are groundedthrough clamping diodes DN to thereby prevent induced voltagegeneration. Electrodes 8, l6, are not grounded but they are distant fromthe electrode 0, and hence do not offer any problem.

FIG. 9 is a circuit diagram of the principal part of another example ofthis invention which is adapted for the impression of positive andnegative voltages and which is characterized in that diodes D1 and D2are utilized for the clamping operation. In the case of selecting theelectrode 0, transistors GP] and QP2 are turned on to flow a current ina charge storage diode CSD2 from a power source l-va and then a positiveaddress voltage is impressed to the electrode 0 from a power source +V.At this time, a transistor QN is turned on, by which nonselectedelectrodes including an adjoining elec trode l are grounded through thediodes D2. In a like manner, in the case of impressing a negativeaddress voltage, transistors QNl and QN2 are turned on to flow a currentin charge storage diodes CSDL towards a power source Va and then thenegative address voltage is impressed from a power source -V. At thistime, the nonselected electrodes including the adjoining electrode l areclamped at the ground potential by turning on a transistor QP4, Wherethe address voltage has thus been impressed to the selected electrode,the nonselected electrodes adjacent to the selected one are grounded, sothat the induced voltage problem can be avoided.

FIG. illustrates another example of this invention in which oddandeven-number electrodes are connected to flexible terminal plates 31A and31B, respectively, at opposite sides of a plasma display panel 30. Atthe time of addressing, a transistor Q5 is turned on and any one oftransistors Q71 to Q74 and Q91 to Q94 is selectively turned on to flow acurrent in the charge storage diode CSD from the power source Va andthen an address voltage is impressed from a power source (not shown) byutilizing the backward recovery time of the diode CSD. For example,where the electrode 4 has been selected, a transistor Q63 is in the offstate but transistors Q61, Q62 and Q64 for for the even-numberelectrodes, or at least transistors Q62 and Q64 adjacent thereto, areturned on and transistors Q81 to Q84 for the odd-number electrodes, orat least transistors Q82 and Q83 connected to electrodes 3 and 5adjacent to the electrode 4, are turned on. Consequently, since at leastthe electrodes 2, 3, 5 and 6 adjacent to the selected electrode 4 aregrounded through the diodes DN, an induced voltage due to the addressvoltage is not established. Further, also in the terminal plates 31A and31B, leads on both sides of that connected to the selected electrode aregrounded to provide the shielding effect, so that where the leads arevery long, the problem of inducing a voltage in the terminal plates isthereby overcome.

A matrix drive circuit by means of which three electrodes on both sidesof the selected electrode are grounded is shown in a schematic form inFIG. 11. In FIG. 11, addressing and clamping diodes are left out anddecoders 40A and 40B are shown as including the inverters 21A and 213,the AND gate 22 and the transistors depicted in FIG. 8 and the chargestorage diodes for the respective electrodes are omitted. Unlike in thecase of FIG. 8, the decoder 40A is supplied with address signals 2, 2and 2 and decoder 40B is supplied with address signals 2 2 and 2.Numerals at the intersecting points indicate electrodes connectedthereto. For example, where the electrode 4 has been selected, only theelectrodes 0, 8, 12, are not clamped but the other electrodes areclamped. Namely, as is apparent from the electrode arrangement diagramshown in DN are disposed adjacent to each other, so that a diode arrayconstruction can be adopted.

In the foregoing examples, at least electrodes adjoining the selectedelectrode are clamped through diodes at the ground potential or apredetermined potential which cancels the induced voltage, therebypreventing the trouble resulting from a voltage which is induced wherethe address voltage such as the write, erasing read or like voltage isimpressed to the selected electrode. A sustain voltage is usuallyimpressed to all of the electrodes but the induced voltage troublepreventing means, described in the foregoing with regard to theexamples, is also applicable to the case of the selective impression ofthe sustain voltage or temporary use of only one part of the plasmadisplay panel for the purpose of overcoming halfselection troubles.Further, the foregoing examples have been described in connection withonly one of the opposing electrodes but it is apparent that the samemeans as described above are employed for the other of the opposingelectrodes.

Referring now to FIG. 13, another example of this invention will bedescribed. FIG. 13 illustrates an address circuit employing chargestorage diodes CSD for the one electrode group of a plasma displaypanel. The electrode groups are represented by four X electrodes X1, X2,X3 and X4. The electrodes. X1, X2, X3 and X4 are respectively connectedto selecting points of a matrix circuit comprising charge storage diodesCSDl, CSD2, CSD4 and diodes Dal, Da2, Da4 and Dbl, Db2, Db4, and theelectrodes are selected by drivers Adl, and A112 and Adll, Adl2respectively.

The above construction is substantially identical with that ofconventional address circuit and positive and negative rectangularsustain voltage pulse trains of Vs are alternately applied to theelectrodes from terminals l and 2. In order to select the electrode, forexample, X1 in the address operation within the time intervals of thesesustain voltage pulse trains, transistors Q1 and Q11 making up theaddress drivers Adl and Adll are turned on by the outputs from a decoder3, flowing a forward current in the charge storage diode CSDl throughthe diode Dal from the power source Va. As a result of this, charge isstored in the charge storage diode CSDl to permit it to conduct inbackward direction only in its recovery time. Accordingly, if atransistor Qw or Qe, respectively, of a write driver 4 or an erasingdriver 5 is further held in its: on state, a write address voltage Vw oran erasing address voltage Ve is applied to the electrode X1 only forthe backward conduction time of the charge storage diode CSDI to performdesired writing or erasing, coupled with the corresponding addressoperation on the side of the Y electrodes (not shown).

The address circuit employing the charge storage diodes CSD isadvantageous in that power dissipation for addressing is small but, onthe other hand, the electrodes other than the selected one are allconnected to high impedance circuits formed by transistors held in theiroff state at the time of addressing, so that the aforementioned inducedvoltage trouble due to the capacitance between adjacent ones of theelectrodes adjoining the selected electrode is unavoidable. If theforegoing example were adapted for eliminating the induced voltagetrouble, the circuit for clamping the adjoining electrodes in accordancewith the selected electrode is appreciably complicated and expensive.

Referring again to FIG. 13, the illustrated example will be described.The selecting points of the matrix circuit, that is, the connectionpoints to the electrodes X1, X2, X4, have connected thereto resistorsR1, R2, R4 at one end respectively. The other ends of the resistors R1,R2, R4 are all interconnected and connected through a diode Dc to thecollector of a clamping transistor Qc. The emitter of the transistor Qcis connected to a clamping power source Vc which is at ground potentialin this case. The base of this transistor is supplied with an addresssignal from a control circuit (not shown) for turning on the transistorQc only at the time of addressing, as is the case with the write anderasing drivers 4 and 5.

With the addition of such a circuit construction as described above, itis possible that, by turning on the clamping transistor Qc at the timeof addressing the selected electrode, all the electrodes are held to begrounded through the resistors and the diodes, in other words, connectedto an appreciably low impedance. As a result of this, even if theaddress voltage Vw or Ve is impressed to the electrode, a high inducedvoltage does not appear in the adjoining electrodes. Namely, theresistors R1, R2, R4 cannot completely reduce the induced voltage tozero but can lower it to such an extent as not to cause misaddressing.

Of course, in this case, one portion of the address voltage Vw or Veapplied to the selected electrode is also consumed by the resistor atits selecting point, so that it is necessary to set the address voltagein anticipation of the added consumption by the resistor. However, thisinvention has advantages that the clamping circuit can be constructed atlow cost, as compared with the system of clamping the adjoiningelectrodes in accordance with the selected electrode, and that theinduced voltage trouble can be effectively avoided.

FIG. 14 is a circuit diagram of the principal part of another example ofthis invention, illustrating some of the X electrodes. A terminal plate51A has formed thereon leads a1, a3, a5, connected to the oddnumberelectrodes X1, X3, X5, of a plasma display panel 50 and conductors ax2,ax4, connected to the even-number electrodes X2, X4, of the panel 50. Ina similar manner, a terminal plate 518 has also formed thereon leads b2,b4, connected to the evennumber electrodes and conductors bxl, bx3,connected to the odd-number electrodes. These leads a1, a3, and b2, b4,have connected thereto drivers 52 respectively to impress the addressvoltage to the selected electrode. The diodes DP and DN are mixingdiodes and the electrodes are connected to clamping circuits 53A and 538through the diodes DP and DN. (Only the circuits connected to theterminal plate 51B are shown, but the terminal plate 51A is identicaltherewith.) The clamping circuits 53A and 53B are provided for clampingthe evenor odd-number electrodes at a predetermined potential in thecase where any of the oddor even-number electrodes has been selected.Transistors QLl and L3 are to clamp the electrodes at Vc and +Vcrespectively and transistors 0L2 and 0L4 are to clamp the electrodes atthe ground potential.

For example, when the electrode X3 has been selected and supplied withthe address voltage inducing positive potentials in the adjacentelectrodes X and X the transistor QLZ is turned on, thereby clamping theadjacent electrodes X2 and X4 to ground potential through the diodes DNand the conducting transistor 0L2. In this case, in the terminal plate51A, the conductors ax2 and ax4, connected to the even-number electrodesx 2 and x4 and disposed on opposite sides of the lead a3, are alsogrounded and, in the terminal plate 51B, the leads b2 and b4 on oppositesides of the conductor bx3 are also similarly grounded, so that theinduced voltage problem as to the electrodes X2 and X4 on opposite sidesof the electrode X3 and the corresponding conductors of both terminalplates can be completely prevented by the shielding efiects of theseconductors. The electrodes X1 and X5 are not grounded but those X2 andX4 adjacent them and the selected electrode X3 respectively aregrounded, so that the resulting induced voltages become very low andthere is substantially no possibility that the induced voltage problemoccurs. Where the voltages induced in the adjoining electrodes X2 and X4are negative, the transistor QL4 of the clamping circuit 538 is turnedon. Further, where the induced voltages are required to be clamped at apredetermined potential, the transistor QLl or QL3 is appropriatelyturned on.

The above description has been given with regard to the case where theodd-number electrode X3 has been selected but also in the case where anyof the evennumber electrodes X2, X4, has been selected, the odd-numberelectrodes X1, X3, are clamped at a predetermined potential such as theground potential or the like by the clamping circuit 53A connected tothe leads a1, a3, of the terminal plate 51A. During the impression ofthe sustain voltage except at the time of addressing, the clampingcircuits 53A and 53B are not operative. Also on the side of the Yelectrodes, the induced voltage problem is prevented in the same manneras that described above.

FIG. 15 illustrates another example of this invention, in whichshielding conductors ax2, 0x4, each disposed between adjacent ones ofthe leads on a terminal plate 61, are not connected to the electrodes ofa plasma display panel 60 but instead are connected together to aclamping circuit 62. The clamping circuit 62 is identical inconstruction with that depicted in FIG. 14 and the leads a1, a3, areshielded by the shielding conductors (1x2, ax4, from each other at thetime of impressing an address voltage such as for writing, erasing,reading or the like. Accordingly, it is possible to prevent the inducedvoltage problem from occuring on the terminal plate 61.

FIG. 16 shows another example of this invention. The cross-section of aterminal plate 71 connected with the electrodes of a plasma displaypanel 70, taken along the line AA in FIG. 16, is shown in FIG. 17A. InFIG. 17A, reference numeral 81 indicates insulating layers, 82 shieldingconductive layers and 83 insulating layers interposed between leads 84and the conductive layers 82. A clamping circuit 72 is connected to theconductive layers 82, by which if an odd-number electrode is selected atthe time of impressing an address voltage such as for writing, erasingor reading, the conductive layers 82 of the terminal plate for the leadsof the evennumber electrodes are clamped at a predetermined potentialsuch, for example, as the ground potential.

FIG. 178 shows, in section, a modified form of the terminal plate, inwhich leads 94 are each surrounded by an insulating layer 93 and arethereby insulated from each other and embedded in a conductor layer 92.Reference numeral 91 designates insulating layers. This constructionprovides for further enhanced shielding effect, as compared with that ofFIG. 17A.

As has been described in the foregoing, in the examples of FIGS. 14 to17, the leads of the terminal plates are divided into those connected tothe odd-number electrodes and those to the even-number electrodes andconnected accordingly, and the conductors disposed near the leads areclamped at a predetermined potential such as the ground potential or thelike. When either one of the odd-or even-number electrodes has beenselected by the impression of the address voltage such as for writing,erasing or reading the conductors disposed adjacent to the leads on theterminal plate having connected thereto the other electrodes areclamped, so that an increase in capacitance due to the adjoiningconductors does not offer any problem during usual sustain voltageimpression and, at the time of impressing the address voltage, theadjoining conductors are clamped by the clamping circuit at the groundpotential or at such a potential as cancelling the induced voltage, thusenabling prevention of the induced voltage problem in the adjoiningelectrodes. This pro vides for enlarged operational margin for thewriting, erasing and reading operations.

FIG. 18 is a circuit diagram of the principal part of still anotherexample of this invention which is suitable for preventing the inducedvoltage problem which occurs in the reading operation of the plasmadisplay panel. FIG. 18 shows only the side of electrodes Y1 to Y4.Sustain voltages +Vs and Vs are alternately applied to all of theelectrodes from sustain voltage circuits 100A and 1008 at all times. Inthe case of reading the state of cells on the electrode, for example,Y2, a read pulse of a voltage V is impressed by turning on a transistor0102 to the electrode Y2 in the time intervals of sustain voltage pulsesand, at the same time, a voltage -V is applied by turning on atransistor Ql to the electrodes Y1 and Y3 adjacent to that Y2. If thevoltage -V is not impressed, erroneous erasure or writing in cells onthe adjoining electrodes is caused by voltages which are induced in theadjoining electrodes at the time of the impression of the read pulse VNamely, the operation becomes unstable. The voltage V is selected at avalue which cancels the influence exerted on the adjoining electrodes bythe voltage V,,. Though different in accordance with the electrodeintervals, the impression voltage or the like, the voltage -V isselected to be, for example, about one-third of the voltage V As is thecase with the foregoing examples, where the read pulse of the voltage Vhas been impressed to the electrode Y3 by turning on a transistor Q104,a transistor 0103 is turned on to apply the voltage -V to the electrodesY2 and Y4. Since the read pulse serving an an address voltage ispositive, the voltage -V opposite in polarity thereto is impressed tothose electrodes adjacent the selected one but where the read pulse isnegative, a voltage +V opposite in polarity thereto is ap plied to theadjacent electrodes.

As in the examples described in the foregoing, also in the case where awrite pulse or an erasing pulse has been impressed, a voltage oppositein polarity thereto is impressed to cancel the electric field acting onthe adjacent electrodes, thereby to remove the undesired influence suchas a change in a wall voltage or the like. The present example has beendescribed in relation to the Y electrodes only but exactly the samemeasures as This invention is not limited specifically to the foregoingexamples but many modifications and variations may be effected withinthe scope defined by the appended claims.

What is claimed is:

1. A system for preventing undesired effects from voltages induced in aplasma display comprising first and second sets of plural electrodesdisposed to intersect each other and define at each such intersection adischarge cell, and wherein circuit means are provided for supplying analternating sustain voltage to said cells, the amplitude of which issufficient only to maintain an existing discharge, and wherein anaddressing voltage applied to a selected electrode of each said firstand second sets serves to establish an address voltage at acorresponding selected cell which exceeds the firing voltage of the celland establishes a discharge therein, and system comprising:

means for applying an addressing voltage to a selected one of theelectrodes of at least one of said first and second sets of electrodes,including, for each electrode,

a first diode having a relatively short charge storage time and a seconddiode having a relatively long charge storage time connected in seriesto said first diode at a junction and commonly poled for conduction,said junction being connected to the electrode, and

means for applying a forward current to said diodes associated with aselected electrode, and means for supplying an addressing voltage to thecathode of said second diode, selectively as to each selected electrode,thereby to apply the addressing voltage to the selected electrode byreverse conduction of said second diode in accordance with thepre-stored charge therein, and means operative simultaneously with saidaddressing voltage means for coupling at least those electrodes disposedimmediately adjacent: a selected electrode to a potential of a levelselected with respect to that of said addressing voltage to suppressvoltages induced in said adjacent electrodes when an addressing voltageis applied to a selected electrode. 2. The system as claimed in claim 1,wherein said coupling means couples a potential to said adjacentelectrodes which is opposite in polarity to that of said addresspotential.

3. The system as claimed in claim 1, wherein said second diode comprisesa charge storage diode.

4. The system as claimed in claim 1, wherein said coupling means couplesa group of electrodes including said selected electrode throughimpedance elements to said selected potential.

5. A system for retarding undesired signals from being induced into aplasma display panel comprising first and second sets of pluralelectrodes disposed to intersect each other and define at each suchintersection a discharge cell, at least said first set of electrodesincluding a first plurality of electrodes spaced from each other and asecond plurality of electrodes interposed between said electrodes ofsaid first plurality, said system comprising:

means for applying an addressing voltage to a selected electrode of oneof said first and second pluralities of electrodes, including, for eachelectrode,

a first diode having a relatively short charge storage time and a seconddiode having a relatively long charge storage time connected in seriesto said first diode at a junction and commonly poled for conduction,said junction being connected to the electrode, and

means for applying a forward current to said diodes associated with aselected electrode, and

means for supplying an addressing voltage to the cathode of said seconddiode, selectively as to each selected electrode, thereby to apply theaddressing voltage to the selected electrode by reverse conduction ofsaid second diode in accordance with the pre-stored charge therein, and

coupling means operative in a first mode when said addressing voltage isapplied to a selected electrode of said first plurality for couplingsaid electrodes of said second plurality of the same said set to apotential of a level selected with respect to that of said addressingvoltage to suppress voltages induced in said electrodes of said secondplurality, and operative in a second mode when an addressing voltage isapplied to a selected electrode of said second plurality for couplingsaid electrodes of said first plurality to said potential of saidselected level.

6. The system as claimed in claim 5, wherein there are included firstand second terminal plates having corresponding first and secondpluralities of leads connected to corresponding ones of said respectivefirst and second pluralities of electrodes.

7. The system as claimed in claim 6, wherein there are further providedfirst and second pluralities of conductors respectively connected tocorresponding electrodes of said first and second pluralities, anddisposed individually between said leads of said second and firsttenninal plates, respectively, said coupling means in said first mode ofoperation further coupling said second plurality of leads to saidselected potential and in said second mode of operation coupling saidfirst pluralityof leads to said selected potential.

8. The system as recited in claim 1 wherein the addressing voltageapplying means further includes, for each electrode,

a series connection of a third and a fourth diode of the types of saidfirst and second diodes, respectively, and poled for common conductionin a reverse sense to said first and second diodes, and furtheraddressing means for applying addressing voltages of opposite polarity,relative to said first named addressing voltages, to the cathode of saidfourth diode and further coupling means for coupling at least the saidadjacent electrodes to said selected potential for suppressing thevoltages induced therein.

9. The system as recited in claim 1 wherein said coupling means includesa unidirectionally conducting element for applying said selectedpotential to said adjacent electrodes.

10. The system as recited in claim 1 wherein said coupling meansincludes impedance elements for applying said selected potential to agroup of said electrodes including a selected electrode.

11. The system as recited in claim 5 wherein said coupling meansincludes means for selective connection to at least the electrodesadjacent a selected electrode of one of said pluralities and at leastthe electrodes of the other of said pluralities adjacent the selectedelectrode of the one said plurality.

12. A system for suppressing undesired signals from being induced into aplasma display panel comprising pluralities of row and column electrodesdisposed on at least one of the inner walls of an envelope to intersecteach other thereby to define at the intersections a correspondingplurality of discharge points across an ionizable gas sealed in theenvelope, the pluralities of row and column electrodes being coveredwith dielectric layers having surfaces in direct contact with theionizable gas, said system comprising:

means connected with said pluralities of row and column electrodes forsupplying each of said plurality of discharge points with analternatingsustain voltage, the level of which is insufficient to produce adischarge by itself but sufficient to maintain a discharge onceproduced;

means connected with said pluralities of row and column electrodes forselectively supplying said plurality of discharge points with an addressvoltage, the level of which is in excess of that of the firing voltagefor a discharge point, said address voltage selective supply meansincluding as to each said electrode a first diode having a relativelyshort charge storage time, a second diode connected in series therewithat a common junction and poled for conduction in the same direction andhaving a relatively long charge storage time, means for connecting saidcommon junction of said diodes to the said electrode, means forselectively applying a forward current to said diodes, and means forselectively connecting an address voltage source to the cathodeof saidsecond diode, the address voltage being applied to said selecteddischarge point by reverse conduction of said second diode in accordancewith charges pre-stored therein; and means for selectively connecting atleast the electrodes adjacent to an electrode associated with a selectedone of said plurality of discharge points to a potential source of sucha polarity as to by-pass voltages induced in said adjacent electrodeswhen an address voltage is applied to said selected discharge point,said connecting means being energized simultaneously with theapplication of said address voltage, thereby to prevent undesirableeffects of the voltages induced in those electrodes adjacent to theselected electrode.

- UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent DatedNovember26, 1974 Inventor) Shozo Umeda; Hiroshi Furuta; Teruo Toba;Hiroshi Goto &

Hiroyuki Shizaki It is certified that error appears in theabove-identifiedpatent and that said Letters Patent are hereby correctedas shown below:

Column 1, line 155, Equation (1) should read: I l

W c1'/(c1 c2 v1 Column 2, line 19, should read:

I v2 =[C1"/ (C1'+ c 2') v1 Column 2, 1ine'2-2, Equatiou (2 sho uld read:v3 c0/(co+c2 v1 Column 9,, li ue 30, should read:

Y4. Sustain voltages +Vs and Vs are alternately applied Signed andsealed this 4th day of February 'i l975 (SEAL) Attest:

McCOY M. GIBSON JR. C. MARSHALL DANN Attesting Officer Commissioner ofPatents

1. A system for preventing undesired effects from voltages induced in a plasma display comprising first and second sets of plural electrodes disposed to intersect each other and define at each such intersection a discharge cell, and wherein circuit means are provided for supplying an alternating sustain voltage to said cells, the amplitude of which is sufficient only to maintain an existing discharge, and wherein an addressing voltage applied to a selected electrode of each said first and second sets serves to establish an address voltage at a corresponding selected cell which exceeds the firing voltage of the cell and establishes a discharge therein, and system comprising: means for applying an addressing voltage to a selected one of the electrodes of at least one of said first and second sets of electrodes, including, for each electrode, a first diode having a relatively short charge storage time and a second diode having a relatively long charge storage time connected in series to said first diode at a junction and commonly poled for conduction, said junction being connected to the electrode, and means for applying a forward current to said diodes associated with a selected electrode, and means for supplying an addressing voltage to the cathode of said second diode, selectively as to each selected electrode, thereby to apply the addressing voltage to the selected electrode by reverse conduction of said second diode in accordance with the pre-stored charge therein, and means operative simultaneously with said addressing voltage means for coupling at least those electrodes disposed immediately adjacent a selected electrode to a potential of a level selected with respect to that of said addressing voltage to suppress voltages induced in said adjacent electrodes when an addressing voltage is applied to a selected electrode.
 2. The system as claimed in claim 1, wherein said coupling means couples a potential to said adjacent electrodes which is opposite in polarity to that of said address potential.
 3. The system as claimed in claim 1, wherein said second diode comprises a charge storage diode.
 4. The system as claimed in claim 1, wherein said coupling means couples a group of electrodes including said selected electrode through impedance elements to said selected potential.
 5. A system for retarding undesired signals from being induced into a plasma display panel comprising first and second sets of plural electrodes disposed to inTersect each other and define at each such intersection a discharge cell, at least said first set of electrodes including a first plurality of electrodes spaced from each other and a second plurality of electrodes interposed between said electrodes of said first plurality, said system comprising: means for applying an addressing voltage to a selected electrode of one of said first and second pluralities of electrodes, including, for each electrode, a first diode having a relatively short charge storage time and a second diode having a relatively long charge storage time connected in series to said first diode at a junction and commonly poled for conduction, said junction being connected to the electrode, and means for applying a forward current to said diodes associated with a selected electrode, and means for supplying an addressing voltage to the cathode of said second diode, selectively as to each selected electrode, thereby to apply the addressing voltage to the selected electrode by reverse conduction of said second diode in accordance with the pre-stored charge therein, and coupling means operative in a first mode when said addressing voltage is applied to a selected electrode of said first plurality for coupling said electrodes of said second plurality of the same said set to a potential of a level selected with respect to that of said addressing voltage to suppress voltages induced in said electrodes of said second plurality, and operative in a second mode when an addressing voltage is applied to a selected electrode of said second plurality for coupling said electrodes of said first plurality to said potential of said selected level.
 6. The system as claimed in claim 5, wherein there are included first and second terminal plates having corresponding first and second pluralities of leads connected to corresponding ones of said respective first and second pluralities of electrodes.
 7. The system as claimed in claim 6, wherein there are further provided first and second pluralities of conductors respectively connected to corresponding electrodes of said first and second pluralities, and disposed individually between said leads of said second and first terminal plates, respectively, said coupling means in said first mode of operation further coupling said second plurality of leads to said selected potential and in said second mode of operation coupling said first plurality of leads to said selected potential.
 8. The system as recited in claim 1 wherein the addressing voltage applying means further includes, for each electrode, a series connection of a third and a fourth diode of the types of said first and second diodes, respectively, and poled for common conduction in a reverse sense to said first and second diodes, and further addressing means for applying addressing voltages of opposite polarity, relative to said first named addressing voltages, to the cathode of said fourth diode and further coupling means for coupling at least the said adjacent electrodes to said selected potential for suppressing the voltages induced therein.
 9. The system as recited in claim 1 wherein said coupling means includes a unidirectionally conducting element for applying said selected potential to said adjacent electrodes.
 10. The system as recited in claim 1 wherein said coupling means includes impedance elements for applying said selected potential to a group of said electrodes including a selected electrode.
 11. The system as recited in claim 5 wherein said coupling means includes means for selective connection to at least the electrodes adjacent a selected electrode of one of said pluralities and at least the electrodes of the other of said pluralities adjacent the selected electrode of the one said plurality.
 12. A system for suppressing undesired signals from being induced into a plasma display panel comprising pluralities of row and column electrodes disposed on at least one of the inner walls of an envelope to intersect each otheR thereby to define at the intersections a corresponding plurality of discharge points across an ionizable gas sealed in the envelope, the pluralities of row and column electrodes being covered with dielectric layers having surfaces in direct contact with the ionizable gas, said system comprising: means connected with said pluralities of row and column electrodes for supplying each of said plurality of discharge points with an alternating sustain voltage, the level of which is insufficient to produce a discharge by itself but sufficient to maintain a discharge once produced; means connected with said pluralities of row and column electrodes for selectively supplying said plurality of discharge points with an address voltage, the level of which is in excess of that of the firing voltage for a discharge point, said address voltage selective supply means including as to each said electrode a first diode having a relatively short charge storage time, a second diode connected in series therewith at a common junction and poled for conduction in the same direction and having a relatively long charge storage time, means for connecting said common junction of said diodes to the said electrode, means for selectively applying a forward current to said diodes, and means for selectively connecting an address voltage source to the cathode of said second diode, the address voltage being applied to said selected discharge point by reverse conduction of said second diode in accordance with charges pre-stored therein; and means for selectively connecting at least the electrodes adjacent to an electrode associated with a selected one of said plurality of discharge points to a potential source of such a polarity as to by-pass voltages induced in said adjacent electrodes when an address voltage is applied to said selected discharge point, said connecting means being energized simultaneously with the application of said address voltage, thereby to prevent undesirable effects of the voltages induced in those electrodes adjacent to the selected electrode. 